This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits (IC) may be formed from arrangements of one or more input/output devices, standard devices, memory devices, and/or the like. In one scenario, memory devices may include memory arrays arranged into memory cells and the associated circuitry to write data to the memory cells and read data from the memory cells. In particular, the memory cells of a memory array, such as a random access memory (RAM) array, may be organized into rows and columns. The logic latches within these individual memory cells may be used to store a data bit that is representative of a logical “1” or “0.” These memory cells may also be interconnected by word-lines (WL) and pairs of complementary bit-lines (BL).
In some scenarios, memory devices with dual ports may be used. The memory arrays of these devices may have two pairs of complementary bit-lines and two word-lines for each memory cell, with each port controlling a respective word-line and pair of complementary bit-lines. In these scenarios, the dual port memory array may allow two memory cells to be accessed in the same memory clock cycle by the use of these different ports, word-lines, and bit-lines.
In a further scenario, the memory array may be vulnerable to errors. For example, write failures and/or read failures may occur in the memory array in certain conditions, such as when the memory array may be operating at lower voltages, higher speeds, and/or smaller topologies. To avoid such failures, one or more write assist or read assist mechanisms may be used with the memory array.